S. Subathradevi ¹, C. Vennila ²

Affiliations
1 A.P. Department of ECE, Anna University, BIT Campus Tiruchirappalli, Tamil Nadu, IN
2 Department of ECE, Saranathan College of Engineering, Tiruchirappalli, Tamil Nadu, IN

Abstract

In VLSI design of system configuration, the important parameter speed is playing a vital role in the design which is purely determined by the delay of the design. In the delay of the design is arrived by design delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more due to miniaturization of the design. During earlier days design delay dominates more. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay in turn optimized speed in trade of with area. In the proposed work, by reviewing different architecture was constructed with different basic module in order to achieve optimized delay which is realized using verilog HDL.

Keywords

Architecture, Distributed Arithmetic, FIR Filter, Parallel Processing, Routing Delay, VLSI Design

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S. Subathradevi ¹, C. Vennila ²

Affiliations
1 A. P. Department of ECE, Anna University, BIT Campus, Tiruchirappalli – 600025, Tamil Nadu, IN
2 Department of ECE, Saranathan College of Engineering, Tiruchirappalli – 620012, TamilNadu, IN

Abstract

In VLSI design of system configuration, among the three important parameters of speed, area and power, the speed is purely determined by the delay of the design. In the delay of the design the design delay is contributed by gate delay and routing i.e. path delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more towards the design delay. Because of scaling in the design, it is essential to concentrate more towards routing delay of the design to get the optimized delay or desired speed of the design with the reduced area. In this work, by studying different architectures constructed with different basic module for binary array multiplier contributes towards the routing delay which can be realized to result in reduced delay.

Keywords

Architecture, Binary Array Multiplier, Path Delay, Routing Delay, VLSI

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